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1 july 1, 2013 IDT82V3911 short form datasheet ? 2013 integrated device technology, inc. dsc-7238/- synchronous ethernet two-channel pll for 10gbe and 40gbe idt and the idt logo are trademarks of integrated device technology, inc. features highlights ? jitter generation <0.3 ps rms (10 khz to 20 mhz), meets jitter requirements of leading phys supporting 10gbase-r, 10gbase- w, 40gbase-r, oc-192 and stm-64 ? supports itu-t g.8261/g.8262 synchronous ethernet (synce) compliant equipment ? supports clock generation for ieee-1588 applications ? generates synce interface clocks (1ge, 10ge, and 40ge) main features ? provides an integrated solution for reference switching, frequency translation and jitter attenuation for synce and sonet/sdh inter- faces ? integrates 2 dplls, one for the transmit path and one for the receive path ? selectable dpll bandwidth: 18 hz and 35 hz ? integrates 2 jitter attenuating aplls to generate ultra-low jitter clocks ? supports 3 clock modes: sonet, ethernet, and ethernet lan- phy ? supports up to two crystal connections, allowing each apll to support up to two modes of operation ? supports input and output clocks covering a wide range of frequen- cies ? provides in3, in4, in7,in6 i nput cmos clocks whose frequen- cies range from 2 khz to 156.25 mhz ? provides in1 and in2 input differ ential clocks whose frequencies range from 2 khz to 625 mhz ? provides out1 to out5 output cmos clocks whose frequency range from 1pps to 125 mhz ? provides out6~out9 output diff erential clocks whose fre- quency range from 25 mhz to 644.53125 mhz ? provides a 1pps, 2 khz, 4 khz, or 8 khz frame sync input signal, and a 1pps, 2 khz or 8 khz frame sync output signal ? supports forced or automatic oper ating mode switch controlled by an internal state machine. automatic mode switch supports free- run, locked and holdover modes ? supports manual and automatic selected input clock switch ? supports automatic hitless selected input clock switch on clock fail- ure ? supports three types of input clo ck sources: recovered clock from stm-n or oc-n, pdh network sy nchronization timing and external synchronization reference timing ? supports lvpecl/lvds and cmos input/output technologies ? supports master clock calibration ? supports telcordia gr-1244-co re, telcordia gr-253-core, itu-t g.812, itu-t g.8262, it u-t g.813 and itu-t g.783 recom- mendations other features ? i2c microprocessor interface ? ieee 1149.1 jtag boundary scan ? single 3.3 v operation with 5 v tolerant cmos i/os ? 1mm ball pitch cabga green package applications ? core and access ip switches / routers ? gigabit and terabit ip switches / routers ? central office timing source and distribution ? dwdm cross-connect and transmission equipment ? ip core routers and access equipment ? cellular and wll base-station node clocks ? broadband and multi-service access equipment
IDT82V3911 short form datasheet synchronous et hernet two-channel pll for 10gbe and 40gbe description 2 july 1, 2013 description the 82v3911 synchronous ethernet (synce) two-channel pll is a jitter attenuating device with rate conversion and reference switching capabilities; its ultra-low jitter output clocks are used to directly synchro- nize 10gbase-r/10gbase-w and oc-192/stm-64 phys and 40gbase-r phys in synchronous ethernet and sonet/sdh equip- ment. when the 82v3911 is locked to a synchronous equipment timing source (sets) that meets the requirements of itu-t g.8262, g.813 or telcordia gr-253-core stratum 3 or sonet minimum clock the clocks generated by the 82v3911 will also meet those requirements. the two 82v3911 timing channels ar e defined by independent digital plls (dplls) with embedded clock synthesizers. the two independent timing channels allow the 82v3911 to synchronize transmit interfaces with the selected system backplane clock, and to simultaneously provide a recovered clock from a selected receive interface to the system back- plane. dpll1 is preferred for synchr onizing transmit interfaces because it has the more sophisticated holdover mode. both dplls support three prim ary operating modes: free-run, locked and holdover. in free-r un mode the dplls generate clocks based on the master clock alone. in locked mode the dplls filter refer- ence clock jitter with one of the following selectable bandwidths: 18 hz or 35 hz. in locked mode the long -term dpll frequency accuracy is the same as the long term frequency accuracy of the selected input refer- ence. in holdover mode the dpll uses frequency data acquired while in locked mode to generate accurate frequencies when input references are not available. the 82v3911 requires a 12.8 mhz ma ster clock for its reference monitors and other digital circuitry. the frequency accuracy of the mas- ter clock determines the frequency ac curacy of the dplls in free-run mode. the frequency stability of the master clock determines the fre- quency stability of the dplls in free-run mode and in holdover mode. the 82v3911 provides four single ended reference inputs and two differential reference inputs that can operate at common ethernet, sonet/sdh and pdh frequencies and other frequencies. the refer- ences are continually monitored for loss of signal and for frequency off- set per user programmed thresholds. al l of the references are available to both dplls. the active reference for each dpll is determined by forced selection or by automatic selection based on user programmed priorities and locking allowances and based on the reference monitors. the 82v3911 can accept a clock reference and a phase locked external sync signal as a pair. dp ll1 can lock to the reference clock input and align its frame sync and mu lti-frame sync outputs with the paired external sync input. the devic e provides to two external sync inputs that can be associated with any of the six reference inputs to cre- ate up to two pairs. the external sync signals can have a frequency of 1 hz, 2 khz or 8 khz. this feature enables dpll1 to phase align its frame sync and multi-frame sync outputs wi th an external sync input without the need use a low bandwidth setting to lock directly to an external sync input. the clocks synthesized by the 82v3911 dplls can be passed through either of the two independent vo ltage controlled cr ystal oscillator (vcxo) based jitter attenuating analog plls (aplls). both aplls drive two independent dividers that have diff erential outputs. the aplls use external crystal resonators with resonant frequencies equal to the apll base frequency divided by 25. both aplls can be provisioned with one or two selectable crystal resonat ors to support up to two base frequen- cies per apll. the output clocks generated by the aplls exhibit jitter below 0.30ps rms over the integration range 10 khz to 20 mhz for most output frequencies.
IDT82V3911 short form datasheet synchronous et hernet two-channel pll for 10gbe and 40gbe functional block diagram 3 july 1, 2013 functional block diagram figure 1. functional block diagram e x _ s y n c 1 m o n i t o r s s y s t e m c l o c k m i c r o p r o c e s s o r i n t e r f a c e j t a g o u t 3 d i v i d e r o u t 4 o u t 5 o u t 2 o u t 1 o s c i a u t o d i v i d e r a u t o d i v i d e r s e l e c t i o n i n p u t i n 1 i n 2 i n 3 i n 4 f r s y n c _ 8 k _ 1 p p s m f r s y n c _ 2 k _ 1 p p s i n p u t p r e - d i v i d e r p r i o r i t y i n p u t p r e - d i v i d e r p r i o r i t y i n p u t p r e - d i v i d e r p r i o r i t y i n p u t p r e - d i v i d e r p r i o r i t y d i v i d e r a p l l 2 e t h g s m / o b s a i / 1 6 e 1 / 1 6 t 1 1 6 e 1 / 1 6 t 1 1 2 e 1 / g p s / e 3 / t 3 7 7 . 7 6 m h z i n p u t s e l e c t o r i n p u t s e l e c t o r e t h g s m / g p s / 1 6 e 1 / 1 6 t 1 1 6 e 1 / 1 6 t 1 1 2 e 1 / 2 4 t 1 / e 3 / t 3 7 7 . 7 6 m h z d i v i d e r d i v i d e r d i v i d e r d i v i d e r d i v i d e r o u t 9 o u t 8 d p l l 2 d p l l 1 a p l l 2 m u x o u t 5 m u x o u t 4 m u x o u t 3 m u x o u t 2 m u x o u t 1 m u x i n _ a p l l 2 e x _ s y n c 2 a p l l 1 d i v i d e r d i v i d e r o u t 6 o u t 7 a p l l 1 m u x i n _ a p l l 1 i n 5 i n 6 i n p u t p r e - d i v i d e r p r i o r i t y i n p u t p r e - d i v i d e r p r i o r i t y d i f f s e s o n e t / g e t h s o n e t / g e t h f r o m d p l l 2 f r o m d p l l 1 f r o m d p l l 2 f r o m d p l l 1 c r y s t a l s e d i f f c r y s t a l
IDT82V3911 datasheet synchronous ethernet two-channel pll for 10gbe and 40gbe pin assignment 4 july 1, 2013 1 pin assignment figure 2. pin assignment (top view) idt co nf iden t ial 1234567891011121314 a ic10 vdda xtal1_in cap1 in_apll1_n eg nc nc tdi ic7 nc osci tms ic6 trst a b ic11 vssa xtal1_out vssao in_apll1_p os nc nc tdo/ ? dpll1_ ? los_lnt vssao tck vssa vssa vssdo vdddo b c ic4 vdda nc cap2 mfrsync_2 k_1pps frsync_8k_ 1pps vdddo vssdo vdda vssa vdda vdda int_req nc c d vssa vssao cap3 vssa vdda nc vssd vddd ic2 vdda vssa vdda out4 out5 d e xtal3_in xtal3_out vssa vssao vssa sonet/sdh vssd vddd ic1 vssa vdda vssa out2 out3 e f vddd vssd vssao vssa vdda vssao vssd vddd vssd vddd ex_sync1 vdddo out1 vssdo f g vssd vddd vssao vssao vssao vssd vddd ic3 vddd vssd ex_sync2 nc nc nc g h vddao vssao vddao vssao vssao vssao vssd vddd vssd vddd nc nc rst in3 h j out6_neg out6_pos vddao vssao vddao vssao vddao vssao vssa vdda dpll1_ ? lock nc in4 in5 j k vssao vssao vssao vddao vssao vddao vssao vssd vddd vssao dpll2_ ? lock in6 i2c_scl i2c_sda k l out7_neg out7_pos vddao vssao vssao vssao vssao i2c_ad1 i2c_ad2 cap4 vssa cap5 vssa cap6 l m vddao vssao vssao vssao vddao vssao vddao vssao vssao vssao vssao nc xtal4_out xtal4_in m n vssao out8_pos vssao out9_pos vssao in_apll2_p os in1_pos in2_pos vssa xtal2_out vssa ic9 vssao vssa n p vddao out8_neg vssao out9_neg vddao in_apll2_n eg in1_neg in2_neg vdda xtal2_in vdda ic8 ic5 vdda p 1234567891011121314 diff ? outputs outputs inputs power ground key:
IDT82V3911 short form datasheet synchronous et hernet two-channel pll for 10gbe and 40gbe pin description 5 july 1, 2013 2 pin description table 1: pin description name pin no. i/o type description 1 global control signal osci a11 i cmos osci: crystal oscillator master clock a nominal 12.8000 mhz clock provided by a crystal oscillator is input on this pin. it is the master clock for the device. sonet/sdh e6 i pull-down cmos sonet/sdh: sonet / sdh frequency selection during reset, this pin determines the default value of the in_sonet_sdh bit (b2, input_mode_cnfg): high: the default value of the in_sonet_sdh bit is ?1? (sonet); low: the default value of the in_sonet_sdh bit is ?0? (sdh). after reset, the value on this pin takes no effect. rst h13 i pull-up cmos rst: reset a low pulse of at least 50 s on this pin resets the device. after this pin is high, the device will still be held in reset state for 500 ms (typical). frame synchronization input signal ex_sync1 f11 i pull-down cmos ex_sync1: external sync input 1 a 2 khz, 4 khz, 8 khz, or 1pps signal is input on this pin. ex_sync2 g11 i pull-down cmos ex_sync2: external sync input 1 a 2 khz, 4 khz, 8 khz, or 1pps signal is input on this pin. input clock in1_pos in1_neg n7 p7 i lvpecl/lvds in1_pos / in1_neg: positive / negative input clock 1 a 2khz, 4khz, n x 8 khz 3 , 1.544 mhz (sonet) / 2.048 mhz (sdh), 6.25 mhz, 6.48 mhz, 10mhz, 19.44 mhz, 25mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz, 125mhz, 155.52 mhz, 156.25 mhz, 311.04 mhz, 312.5 mhz, 622.08 mhz or 625 mhz clock is differentially input on this pair of pins. whether the clock signal is lvpecl or lvds is automatically detected. single-ended input for differential input is also supported. refer to chapter 7.3.2.5 sin- gle-ended input for differential input . in2_pos in2_neg n8 p8 i lvpecl/lvds in2_pos / in2_neg: positive / negative input clock 2 a 2khz, 4khz, n x 8 khz 3 , 1.544 mhz (sonet) / 2.048 mhz (sdh), 6.25 mhz, 6.48 mhz, 10mhz, 19.44 mhz, 25mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz, 125mhz, 155.52 mhz, 156.25 mhz, 311.04 mh z or 312.5 mhz, 622.08 mhz or 625 mhz clock is differentially input on this pair of pins. whether the clock signal is lvpecl or lvds is automatically detected. single-ended input for differential input is also supported. refer to chapter 7.3.2.5 sin- gle-ended input for differential input . in3 h14 i pull-down cmos in3: input clock 3 a 2khz, 4khz, n x 8 khz 3 , 1.544 mhz (sonet) / 2.048 mhz (sdh), 6.25 mhz, 6.48 mhz, 10mhz, 19.44 mhz, 25mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz, 125mhz, 155.52 mhz or 156.25 mhz clock is input on this pin. in4 j13 i pull-down cmos in4: input clock 4 a 2khz, 4khz, n x 8 khz 3 , 1.544 mhz (sonet) / 2.048 mhz (sdh), 6.25 mhz, 6.48 mhz, 10mhz, 19.44 mhz, 25mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz, 125mhz, 155.52 mhz or 156.25 mhz clock is input on this pin. in5 j14 i pull-down cmos in5: input clock 5 a 2khz, 4khz, n x 8 khz 3 , 1.544 mhz (sonet) / 2.048 mhz (sdh), 6.25 mhz, 6.48 mhz, 10mhz, 19.44 mhz, 25mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz, 125mhz, 155.52 mhz or 156.25 mhz clock is input on this pin.
IDT82V3911 short form datasheet synchronous et hernet two-channel pll for 10gbe and 40gbe pin description 6 july 1, 2013 in6 k12 i pull-down cmos in6: input clock 6 a 2khz, 4khz, n x 8 khz 3 , 1.544 mhz (sonet) / 2.048 mhz (sdh), 6.25 mhz, 6.48 mhz, 10mhz, 19.44 mhz, 25mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz, 125mhz, 155.52 mhz or 156.25 mhz clock is input on this pin. in_apll1_pos in_apll1_neg b5 a5 i pull-down i pull-up/ pull-down lvpecl/lvds/ lvhstl/sstl/ hcsl in_apll1_pos / in_apll1_neg: input clock to apll1 direct input clock to apll1. this pin is used for test. it can be left floating or a 1k ? resistor can be tied from in_apll1_pos to ground. in_apll2_pos in_apll2_neg n6 p6 i pull-down i pull-up/ pull-down lvpecl/lvds/ lvhstl/sstl/ hcsl in_apll2_pos / in_apll2_neg: input clock apll2 direct input clock to apll2. this pin is used for test. it can be left floating or a 1k ? resistor can be tied from in_apll1_pos to ground. output frame synchronization signal frsyn- c_8k_1pps c6 o cmos frsync_8k_1pps: 8 khz frame sync output an 8 khz signal or a 1pps fram e pulse is output on this pin. mfrsyn- c_2k_1pps c5 o cmos mfrsync_2k_1pps: 2 khz multiframe sync output a 2 khz signal or a 1pps frame pulse is output on this pin. output clock out1 out2 out3 out4 out5 f13 e13 e14 d13 d14 ocmos out1 ~ out5: output clock 1 ~ 5 a 1 pps, 400 hz, 2 khz, 8 khz, 64 khz, n x e1 4 , n x t1 5 , n x 13.0 mhz 6 , n x 3.84 mhz 7 , 5 mhz, 10 mhz, 20 mhz, e3, t3, 6.48 mhz, 19.44 mhz, 25.92 mhz, 38.88 mhz, 51.84 mhz, 77.76 mhz, 25mhz, or 125 mhz clock is output on these pins. out6_pos out6_neg j2 j1 o lvpecl/lvds out6_pos / out6_neg: positive / negative output clock 6 a sonet based (77.76 mhz, 155.52 mhz, 311.04 mhz, 622.08 mhz), ethernet based (25 mhz, 125 mhz, 156.25 mhz, 312.5 mhz, 625 mhz), or ethernet lan based (161.1328125 mhz, 322.265625 mhz, 644.53125 mhz) clock is differentially output on this pair of pins from apll1. out7_pos out7_neg l2 l1 o lvpecl/lvds out7_pos / out7_neg: positive / negative output clock 7 a sonet based (77.76 mhz, 155.52 mhz, 311.04 mhz, 622.08 mhz), ethernet based (25 mhz, 125 mhz, 156.25 mhz, 312.5 mhz, 625 mhz), or ethernet lan based (161.1328125 mhz, 322.265625 mhz, 644.53125 mhz) clock is differentially output on this pair of pins from apll1. out8_pos out8_neg n2 p2 o lvpecl/lvds out8_pos / out8_neg: positive / negative output clock 8 a sonet based (77.76 mhz, 155.52 mhz, 311.04 mhz, 622.08 mhz), ethernet based (25 mhz, 125 mhz, 156.25 mhz, 312.5 mhz, 625 mhz), or ethernet lan based (161.1328125 mhz, 322.265625 mhz, 644.53125 mhz) clock is differentially output on this pair of pins from apll2. out9_pos out9_neg n4 p4 o lvpecl/lvds out9_pos / out9_neg: positive / negative output clock 9 a sonet based (77.76 mhz, 155.52 mhz, 311.04 mhz, 622.08 mhz), ethernet based (25 mhz, 125 mhz, 156.25 mhz, 312.5 mhz, 625 mhz), or ethernet lan based (161.1328125 mhz, 322.265625 mhz, 644.53125 mhz) clock is differentially output on this pair of pins from apll2. miscellaneous cap1, cap2, cap3 a4, c4, d3 o analog cap1, cap2 and cap3: analog power filter capacitor connection 1 to 3 connect a 10uf capacitor in parallel with a low esr 100nf capacitor between these pins and vss1 cap4, cap5, cap6 l10, l12, l14 o analog cap4, cap5 and cap6: analog power filter capacitor connection 4 to 6 connect a 10uf capacitor in parallel with a low esr 100nf capacitor between these pins and vss2 table 1: pin description (continued) name pin no. i/o type description 1
IDT82V3911 short form datasheet synchronous et hernet two-channel pll for 10gbe and 40gbe pin description 7 july 1, 2013 xtal1_in a3 i analog crystal oscillator 1 input. determines first of two frequency families (sonet/sdh, ethernet or ethernet*66/64) available for apll1. connect to ground if xtal1 is not used. xtal1_out b3 o analog crystal oscillator 1 output. leave open if xtal1 is not used. xtal2_in p10 i analog crystal oscillator 2 input. determines first of two frequency families (chosen from sonet/sdh, ethernet or ether- net*66/64) available for apll2. connect to ground if xtal2 is not used xtal2_out n10 o analog crystal oscillator 2 output. leave open if xtal2 is not used. xtal3_in e1 i analog crystal oscillator 3 input. determines second of two frequency families (chosen from sonet/sdh, ethernet or ethernet*66/64) available for apll1. connect to ground if xtal3 is not used. xtal3_out e2 o analog crystal oscillator 3 output. leave open if xtal3 is not used. xtal4_in m14 i analog crystal oscillator 4 input. connect to ground if xtal4 is not used. determines second of two frequency families (chosen from sonet/sdh, ethernet or ethernet*66/64) available for apll2. xtal4_out m13 o analog crystal oscillator 4 output. leave open if xtal4 is not used. lock indication signals dpll2_lock k11 o cmos dpll2 lock indicator. this pin goes high when dpll2 is locked. dpll1_lock j11 o cmos dpll1 lock indicator. this pin goes high when dpll1 is locked. microprocessor interface int_req c13 o cmos int_req: interrupt request this pin is used as an interrupt request. the output characteristics are determined by the hz_en bit (b1, interrupt_cnfg) and the int_pol bit (b0, inter- rupt_cnfg). i2c_sda k14 i/o pull-down cmos i2c_sda: serial data input/output this pin is used as the input/output for the i2c serial data. i2c_ad1 l8 i pull-up cmos i2c_ad1: device address bit 1 i2c_ad2 and i2c_ad1 pins are the address bus of the microprocessor interface. i2c_ad2 l9 i pull-up cmos i2c_ad2: device address bit 2 i2c_ad2 and i2c_ad1 pins are the address bus of the microprocessor interface. i2c_scl k13 i pull-down cmos i2c_scl: serial clock line the i2c serial clock is input on this pin. jtag (per ieee 1149.1) trst a14 i pull-down cmos trst: jtag test reset (active low) a low signal on this pin resets the jtag test port. this pin should be connected to ground when jtag is not used. tms a12 i pull-up cmos tms: jtag test mode select the signal on this pin controls the jtag test performance and is sampled on the rising edge of tck. tck b10 i pull-down cmos tck: jtag test clock the clock for the jtag test is input on this pin. tdi and tms are sampled on the rising edge of tck and tdo is updated on the falling edge of tck. if tck is idle at a low level, all stored-state devices contained in the test logic will indefi- nitely retain their state. tdi a8 i pull-up cmos tdi: jtag test data input the test data is input on this pin. it is clocked into the device on the rising edge of tck. table 1: pin description (continued) name pin no. i/o type description 1
IDT82V3911 short form datasheet synchronous et hernet two-channel pll for 10gbe and 40gbe pin description 8 july 1, 2013 tdo/ dpll1_los_int b8 o cmos tdo: jtag test data output the test data is output on this pin. it is clocked out of the device on the falling edge of tck. tdo pin outputs a high impedance signal except during the process of data scanning. dpll1_los_int: dpll1 los interrupt this pin can indicate the interrupt of dpll1 selected input clock fail, as determined by the los_flag_on_tdo bit (b6, mon_sw_hs_cnfg). refer to chapter 3.8.1 input clock validity for details. power & ground vddd d8, e8, f1, f8, f10, g2, g7, g9, h8, h10, k9 power - digital core power - +3.3v dc nominal vdddo b14, c7, f12 power digital output power - +3.3v dc nominal vdda a2, c2, c9, c11, c12, d5, d10, d12, e11, f5, j10, p9, p11, p14 power analog core power - +3.3v dc nominal vddao h1, h3, j3, j5, j7, k4, k6, l3, m1, m5, m7, p1, p5 power analog output power - +3.3v dc nominal vssd d7, e7, f2, f7, f9, g1, g6, g10, h7, h9, k8 ground - ground vssdo b13, c8, f14 ground - ground vssa b2, b11, b12, c10, d1, d4, d11, e3, e5, e10, e12, f4, j9, l11, l13, n9, n11, n14 ground - analog ground vssao b4, b9, d2, e4, f3, f6,g3, g4, g5, h2, h4, h5, h6, j4, j6, j8, k1, k2, k3, k5,k7, k10, l4, l5, l6, l7, m2, m3, m4, m6, m8, m9, m10, m11, n1, n3, n5, n13, p3 ground - analog output ground table 1: pin description (continued) name pin no. i/o type description 1
IDT82V3911 short form datasheet synchronous et hernet two-channel pll for 10gbe and 40gbe pin description 9 july 1, 2013 others ic1 ic2 ic3 ic4 ic5 ic6 ic7 ic8 ic9 ic10 ic11 e9 d9 g8 c1 p13 a13 a9 p12 n12 a1 b1 -- ic: internal connected internal use. these pins should be left open for normal operation. nc a6, a7, a10, b6, b7, c3 c14, d6 g12, g13, g14, h11, h12, j12, m12 -- nc: not connected not connected: there is no internal connection to these pins note: 1. all the unused input pins should be connected to ground; the output of all the unused output pins are don?t-care. 2. the contents in the brackets indicate the position of the register bit/bits. 3. n x 8 khz: 1 < n < 19440. 4. n x e1: n = 1, 2, 3, 4, 6, 8, 12, 16 5. n x t1: n = 1, 2, 3, 4, 6, 8, 12, 16, 24 6. n x 13.0 mhz: n = 1, 2 7. n x 3.84 mhz: n = 1, 2, 4, 8 table 1: pin description (continued) name pin no. i/o type description 1
IDT82V3911 short form datasheet synchronous et hernet two-channel pll for 10gbe and 40gbe recommendations for unused input and output pins 10 july 1, 2013 2.1 recommendations for unu sed input and output pins 2.1.1 inputs control pins all control pins have internal pul l-ups or pull-downs ; additional resis- tance is not required but can be added for additional protection. a 1k resistor can be used. single-ended clock inputs for protection, unused single- ended clock inputs should be tied to ground. differential clock inputs for applications not requiring the use of a differential input, both *_pos and *_neg can be left floating. though not required, but for additional protection, a 1k resistor can be tied from _pos to ground. xtal inputs for applications not requiring the us e of a crystal oscillator input, both _in and _out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from _in to ground. 2.1.2 outputs status pins for applications not requiring the use of a status pin, we recommend bringing out to a test point for debugging purposes. single-ended clock outputs all unused single-ended clock outputs can be left floating, or can be brought out to a test point for debugging purposes. differential clock outputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
IDT82V3911 short form datasheet synchronous et hernet two-channel pll for 10gbe and 40gbe 11 july 1, 2013 ordering information xxxxxxx xx x device type blank process / temperature range 82v3911 industrial (- 40 c to + 85 c) aug 196 ball 15mm x 15mm cabga package
IDT82V3911 short form datasheet synchronous ethern et two-channel pll for 10gbe and 40gbe 12 july 1, 2013 disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at id t?s sole discretion. all information in this doc- ument, including descriptions of product feat ures and performance, is subject to cha nge without notice. performance specificati ons and the operating parameters of the described products are deter mined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provide d without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an implied warranty of merchantability, or non-infrin gement of the intellectual propert y rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly af fect the health or safety of users. anyone using an idt product in such a manner does so at their ow n risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support tsd@idt.com +480-763-2056 we?ve got your timing solution

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